1. Field of the invention
The present invention relates generally to integrated circuits and, in particular, to a method of generating multiple frequency clock signals in an integrated circuit.
2. Description of Related Art
Integrated circuits typically include multiple logic devices packaged in a single assembly ("chip"). Each logic device, in turn, comprises one or more logic elements such as gates or single memory elements. Each logic element operates at a given frequency determined by a clock signal. In the context of digital circuits, a clock is a circuit that emits a series of pulses with a precise pulse width and a precise interval between consecutive pulses. Thus, during a pulse a first predetermined voltage, i.e., an active signal is present on a line on which the clock signal is provided, e.g., the signal is high, while at all other times, a second predetermined voltage, e.g., an inactive signal, either no voltage, or a voltage lower than the first predetermined voltage, is present on the line e.g., the signal is low. The transition from the low state to the high state of the signal is referred to as a rising edge of the clock signal, while a transition from the high state of the signal to the low state of the signal is referred to as a falling edge of the clock signal. The interval between consecutive corresponding edges of the clock signal i.e., either between consecutive rising edges or between consecutive falling edges, is the cycle time of the clock signal. The number of cycles of the clock signal occurring in a fixed period of time is the frequency of the clock signal. The duty cycle of a clock signal is the percentage of clock cycle time during which the signal is high, in the example.
To allow synchronization of the operations performed by different logic elements, typically one or more input clock signals are provided which serve as a reference clock signal for all logic elements in the integrated circuit. A logic element may operate at lower or higher frequency than the input clock signal, but its timing relationship to other logic elements is defined in relationship to the timing of the input clock signal.
In some applications, certain logic elements need to operate at a high frequency, while other logic elements only need to operate at a low frequency. Thus, if a single clock signal is provided for all logic elements, the clock signal must have at least the same frequency as the highest frequency required by any logic element in the integrated circuit. However, this results in unnecessary power consumption and increases both the logic area required to accommodate tighter timing constraints and the functional complexity of the logic devices required for high frequency operation.
It is thus desirable to provide multiple frequency clock signals in a single integrated circuit, or a portion of an integrated circuit, having a single input clock. Prior art methods to provide multiple frequency clock signals, however, present several limitations.
An obvious technique for dividing down the input clock signal frequency for each lower frequency output clock signal is to use a counter clocked by the input clock of the integrated circuit. Using this approach, however, the path from an input terminal on which the input clock signal is received to each of the output terminals on which the lower frequency clock signals are provided is routed through a register, whereas the input clock signal is not. As a result, the delay caused by routing the lower frequency output clock signals through registers make it difficult to synchronize the input clock signal with the lower frequency clock signals across the operating range (supply voltage, temperature and integrated circuit process variation) of the integrated circuit.
The synchronization problem can be avoided by using an input clock signal that has a frequency that is twice the desired frequency of the fastest output clock signal. A counter is then used to divide down the frequency of the input clock signal for each output clock signal. Since the delay introduced by the counter is approximately the same for all output clock signals, the output clock signals can be synchronized. The higher frequency source, however, consumes more power and may require the use of an expensive integrated circuit fabrication process.
Another alternative is to gate or mask out some of the input clock signal pulses to generate a lower frequency output clock signal with a duty cycle which is a either a multiple or a fraction of the duty cycle of the input clock signal. FIG. 1 shows the timing for such an implementation for three clock signals, C1, C2a and C2b, where clock signal C1 has the same frequency as the input clock CIN and clock signals C2a and C2b have half the frequency of the input clock signal CIN. Clock signal C1 is generated by routing input clock signal CIN through a logical AND gate together with a logical one signal. Clock signal C2a is generated by routing input clock signal CIN through a logical AND gate together with a masking signal. Clock signal C2b is generated by routing input clock signal CIN and a masking signal through a logical OR gate. Since the delay introduced by the logical AND/OR gates is roughly the same for output clock signals C1, C2a and C2b, this technique allows the output clocks to be synchronized. However, clock signals C2a and C2b have different duty cycles than input clock signal CIN (approximately 25% and 75%, respectively). This may not be suitable for logic elements which require a duty cycle of approximately 50%.
There is thus a need for an improved method and apparatus for generating multiple frequency clock signals.